Horton

Re: [PATCH] Fix ARM64/MSVC atomic memory ordering issues on Win11 by adding explicit DMB ?barriers

Nathan Bossart <nathandbossart@gmail.com>

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From: Nathan Bossart <nathandbossart@gmail.com>
To: Greg Burd <greg@burd.me>
Cc: Thomas Munro <thomas.munro@gmail.com>, PostgreSQL Hackers <pgsql-hackers@lists.postgresql.org>, Peter Eisentraut <peter@eisentraut.org>, Dave Cramer <davecramer@gmail.com>, Andres Freund <andres@anarazel.de>
Date: 2025-12-12T16:03:01Z
Lists: pgsql-hackers

Commits

Same data as JSON: GET /api/v1/messages/:b64id/commits the thread's linked commits as JSON, with link sources. API reference →

  1. MSVC: Support building for AArch64.

+/*
+ * _InterlockedExchange() generates a full memory barrier (or release
+ * semantics that ensures all prior memory operations are visible to
+ * other cores before the lock is released.
+ */
+#define S_UNLOCK(lock) (InterlockedExchange(lock, 0))

This seems to change the implementation from

	#define S_UNLOCK(lock)	\
		do { _ReadWriteBarrier(); (*(lock)) = 0; } while (0)

in some cases, but I am insufficiently caffeinated to figure out what
platforms use which implementation.  In any case, it looks like we are
changing it for some currently-supported platforms, and I'm curious why.
Perhaps there's some way to make the #ifdefs a bit more readable, too
(e.g., a prerequisite patch that rearranges things).

The rest looks generally reasonable to me.

-- 
nathan