Re: Reduce timing overhead of EXPLAIN ANALYZE using rdtsc?

John Naylor <johncnaylorls@gmail.com>

From: John Naylor <johncnaylorls@gmail.com>

To: Lukas Fittl <lukas@fittl.com>

Cc: Andres Freund <andres@anarazel.de>, Jakub Wartak <jakub.wartak@enterprisedb.com>, Hannu Krosing <hannuk@google.com>, Robert Haas <robertmhaas@gmail.com>, Pavel Stehule <pavel.stehule@gmail.com>, vignesh C <vignesh21@gmail.com>, Michael Paquier <michael@paquier.xyz>, Ibrar Ahmed <ibrar.ahmad@gmail.com>, Maciek Sakrejda <m.sakrejda@gmail.com>, pgsql-hackers <pgsql-hackers@postgresql.org>, David Geier <geidav.pg@gmail.com>

Date: 2026-04-03T09:06:14Z

Lists: pgsql-hackers

On Fri, Apr 3, 2026 at 6:16 AM Lukas Fittl <lukas@fittl.com> wrote:
> v16

Just some minor quibbles on 0002:

--- a/src/include/port/pg_cpu.h
+++ b/src/include/port/pg_cpu.h
@@ -23,6 +23,12 @@ typedef enum X86FeatureId
  /* scalar registers and 128-bit XMM registers */
  PG_SSE4_2,
  PG_POPCNT,
+ PG_HYPERVISOR,

The hypervisor flag doesn't really belong with an instruction family.
Maybe a separate category like "identification"?

+ /* TSC flags */
+ PG_RDTSCP,
+ PG_TSC_INVARIANT,
+ PG_TSC_ADJUST,

Maybe spell out time stamp counter in the comment, since this will be
the first time the reader encounters that in this file.

+ * For some other Hypervisors that have an invariant TSC, e.g. HyperV, we would
+ * need to access an MSR to get the frequency (which is typically not available

Maybe spell out MSR too, because I for one don't know what that is.

+ X86Features[PG_HYPERVISOR] = reg[ECX] >> 31 & 1;
+ have_osxsave = reg[ECX] & (1 << 27);
+
+ pg_cpuid_subleaf(0x07, 0, reg);
+
+ X86Features[PG_TSC_ADJUST] = (reg[EBX] & (1 << 1)) != 0;

Some inconsistency in shift style.

-- 
John Naylor
Amazon Web Services

Commits

Same data as JSON: GET /api/v1/messages/:b64id/commits the thread's linked commits as JSON, with link sources. API reference →

pg_test_timing: Show additional TSC clock source debug info
- 5ba34f6dc838 19 (unreleased) landed
instrumentation: Avoid CPUID 0x15/0x16 for Hypervisor TSC frequency
- 7fc36c5db550 19 (unreleased) landed
pg_test_timing: Also test RDTSC[P] timing, report time source, TSC frequency
- 16fca4825483 19 (unreleased) landed
Allow retrieving x86 TSC frequency/flags from CPUID
- bcb2cf41f964 19 (unreleased) landed
instrumentation: Standardize ticks to nanosecond conversion method
- 0022622c93d9 19 (unreleased) landed
instrumentation: Use Time-Stamp Counter on x86-64 to lower overhead
- 294520c44487 19 (unreleased) landed
Check for __cpuidex and __get_cpuid_count separately
- effaa464afd3 19 (unreleased) landed
pg_test_timing: Reduce per-loop overhead
- 82c0cb4e672d 19 (unreleased) landed
Refactor handling of x86 CPUID instructions
- be6a7494d2e3 19 (unreleased) landed
instrumentation: Drop INSTR_TIME_SET_CURRENT_LAZY macro
- 9d6294c09ed0 19 (unreleased) landed
Rename pg_crc32c_sse42_choose.c for general purpose
- b9278871f991 19 (unreleased) cited
Zero initialize uses of instr_time about to trigger compiler warnings
- 25b2aba0c3a5 16.0 landed
instr_time: Represent time as an int64 on all platforms
- 03023a2664f8 16.0 landed
Add 250c8ee07ed to git-blame-ignore-revs
- ff23b592ad66 16.0 cited