Re: SLRU optimization - configurable buffer pool and partitioning the SLRU lock

Tender Wang <tndrwang@gmail.com>

From: tender wang <tndrwang@gmail.com>
To: "Andrey M. Borodin" <x4mmm@yandex-team.ru>
Cc: Amul Sul <sulamul@gmail.com>, Dilip Kumar <dilipbalaut@gmail.com>, Alvaro Herrera <alvherre@alvh.no-ip.org>, PostgreSQL Hackers <pgsql-hackers@lists.postgresql.org>
Date: 2023-12-14T09:28:01Z
Lists: pgsql-hackers
Andrey M. Borodin <x4mmm@yandex-team.ru> 于2023年12月14日周四 17:02写道:

>
>
> > On 14 Dec 2023, at 08:12, Amul Sul <sulamul@gmail.com> wrote:
> >
> >
> > + int bankno = pageno & ctl->bank_mask;
> >
> > I am a bit uncomfortable seeing it as a mask, why can't it be simply a
> number
> > of banks (num_banks) and get the bank number through modulus op (pageno %
> > num_banks) instead of bitwise & operation (pageno & ctl->bank_mask)
> which is a
> > bit difficult to read compared to modulus op which is quite simple,
> > straightforward and much common practice in hashing.
> >
> > Are there any advantages of using &  over % ?
>

use Compiler Explorer[1] tool, '%' has more Assembly instructions than '&'
.
int GetBankno1(int pageno) {
    return pageno & 127;
}

int GetBankno2(int pageno) {
    return pageno % 127;
}
under clang 13.0
GetBankno1:                             # @GetBankno1
        push    rbp
        mov     rbp, rsp
        mov     dword ptr [rbp - 4], edi
        mov     eax, dword ptr [rbp - 4]
        and     eax, 127
        pop     rbp
        ret
GetBankno2:                             # @GetBankno2
        push    rbp
        mov     rbp, rsp
        mov     dword ptr [rbp - 4], edi
        mov     eax, dword ptr [rbp - 4]
        mov     ecx, 127
        cdq
        idiv    ecx
        mov     eax, edx
        pop     rbp
        ret
under gcc 13.2
GetBankno1:
        push    rbp
        mov     rbp, rsp
        mov     DWORD PTR [rbp-4], edi
        mov     eax, DWORD PTR [rbp-4]
        and     eax, 127
        pop     rbp
        ret
GetBankno2:
        push    rbp
        mov     rbp, rsp
        mov     DWORD PTR [rbp-4], edi
        mov     eax, DWORD PTR [rbp-4]
        movsx   rdx, eax
        imul    rdx, rdx, -2130574327
        shr     rdx, 32
        add     edx, eax
        mov     ecx, edx
        sar     ecx, 6
        cdq
        sub     ecx, edx
        mov     edx, ecx
        sal     edx, 7
        sub     edx, ecx
        sub     eax, edx
        mov     ecx, eax
        mov     eax, ecx
        pop     rbp
        ret


[1] https://godbolt.org/

The instruction AND is ~20 times faster than IDIV [0]. This is relatively
> hot function, worth sacrificing some readability to save ~ten nanoseconds
> on each check of a status of a transaction.
>

  Now that AND is more faster, Can we  replace the '% SLRU_MAX_BANKLOCKS'
operation in  SimpleLruGetBankLock()  with '& 127' :
  SimpleLruGetBankLock()
{
       int banklockno = (pageno & ctl->bank_mask) % SLRU_MAX_BANKLOCKS;

   use '&'
       return &(ctl->shared->bank_locks[banklockno].lock);
}
Thoughts?

>
> [0] https://www.agner.org/optimize/instruction_tables.pdf
>
>

Commits

  1. Fix zeroing of pg_serial page without SLRU bank lock

  2. Fix misspelled assertions

  3. GUC table: Add description to computed variables

  4. Improve performance of subsystems on top of SLRU

  5. Rename SLRU elements in view pg_stat_slru

  6. Use atomic access for SlruShared->latest_page_number

  7. Split use of SerialSLRULock, creating SerialControlLock

  8. Index SLRUs by 64-bit integers rather than by 32-bit integers

  9. Add a macro templatized hashtable.