Re: Remove last traces of HPPA support

Tom Lane <tgl@sss.pgh.pa.us>

From: Tom Lane <tgl@sss.pgh.pa.us>
To: Andres Freund <andres@anarazel.de>
Cc: Noah Misch <noah@leadboat.com>, Thomas Munro <thomas.munro@gmail.com>, pgsql-hackers@lists.postgresql.org
Date: 2023-10-20T21:46:59Z
Lists: pgsql-hackers
Andres Freund <andres@anarazel.de> writes:
> On 2023-10-20 15:59:42 -0400, Tom Lane wrote:
>> Hmm, are you saying there's more of port/atomics/ that could be
>> removed?  What exactly?

> I was thinking we could remove the whole fallback path for atomic operations,
> but it's a bit less, because we likely don't want to mandate support for 64bit
> atomics yet.

Yeah.  That'd be tantamount to desupporting 32-bit arches altogether,
I think.  I'm not ready to go there yet.

> That'd still allow removing more than half of
> src/include/port/atomics/fallback.h and src/backend/port/atomics.c - and more
> if we finally decided to require a spinlock implementation.

In the wake of 1c72d82c2, it seems likely that requiring some kind of
spinlock implementation is not such a big lift.  Certainly, a machine
without that hasn't been a fit target for production in a very long
time, so maybe we should just drop that semaphore-based emulation.

>> Do we really want to assume that all future architectures will have atomic
>> operations?

> Yes. Outside of the tiny microcontrollers, which obviously won't run postgres,
> I cannot see any future architecture not having support for atomic operations.

I'd like to refine what that means a bit more.  Are we assuming that
a machine providing any of the gcc atomic intrinsics (of a given
width) will provide all of them?  Or is there a specific subset that
we can emulate the rest on top of?

			regards, tom lane



Commits

  1. Require memory barrier support.

  2. Require compiler barrier support.

  3. Remove --disable-atomics, require 32 bit atomics.

  4. Remove --disable-spinlocks.

  5. Remove support for HPPA (a/k/a PA-RISC) architecture.

  6. Add a basic atomic ops API abstracting away platform/architecture details.