Re: Atomic operations within spinlocks
Andres Freund <andres@anarazel.de>
From: Andres Freund <andres@anarazel.de>
To: Tom Lane <tgl@sss.pgh.pa.us>
Cc: Robert Haas <robertmhaas@gmail.com>, pgsql-hackers@lists.postgresql.org
Date: 2020-06-06T03:32:32Z
Lists: pgsql-hackers
Hi, On 2020-06-05 22:52:47 -0400, Tom Lane wrote: > Andres Freund <andres@anarazel.de> writes: > > On 2020-06-05 21:01:56 -0400, Tom Lane wrote: > >> At some point I think we'll have to give up --disable-spinlocks; it's > >> really of pretty marginal use (how often does anyone port PG to a new > >> CPU type?) and the number of weird interactions it adds in this area > >> seems like more than it's worth. > > > Indeed. And any new architecture one would port PG to would have good > > enough compiler intrinsics to make that trivial. I still think it'd make > > sense to have a fallback implementation using compiler intrinsics... > > > And I think we should just require 32bit atomics at the same time. Would > > probably kill gaur though. > > Not only gaur. A quick buildfarm survey finds these active members > reporting not having 32-bit atomics: Hm, I don't think that's the right test. We have bespoke code to support most of these, I think: > anole | 2020-06-05 11:20:17 | pgac_cv_gcc_atomic_int32_cas=no Has support via acc specific intrinsics. > chipmunk | 2020-05-29 22:27:56 | pgac_cv_gcc_atomic_int32_cas=no Doesn't have support for __atomic, but does have support for 32bit __sync. > gharial | 2020-06-05 12:41:14 | pgac_cv_gcc_atomic_int32_cas=no __sync support for both 32 and 64 bit. > curculio | 2020-06-05 22:30:06 | pgac_cv_gcc_atomic_int32_cas=no > frogfish | 2020-05-31 13:00:25 | pgac_cv_gcc_atomic_int32_cas=no __sync support for both 32 and 64 bit. > mandrill | 2020-06-05 09:20:03 | pgac_cv_gcc_atomic_int32_cas=no __sync support for 32, as well as as inline asm for 32bit atomics (although we might be able to add 64 bit). > hornet | 2020-06-05 09:11:26 | pgac_cv_gcc_atomic_int32_cas=no > hoverfly | 2020-06-05 22:06:14 | pgac_cv_gcc_atomic_int32_cas=no __sync support for both 32 and 64 bit, and we have open coded ppc asm. > locust | 2020-06-05 10:14:29 | pgac_cv_gcc_atomic_int32_cas=no > prairiedog | 2020-06-05 09:55:49 | pgac_cv_gcc_atomic_int32_cas=no Wee, these don't have __sync? But I think it should be able to use the asm ppc implementation for 32 bit atomics. > gaur | 2020-05-19 13:33:25 | pgac_cv_gcc_atomic_int32_cas=no As far as I understand pa-risc doesn't have any atomic instructions except for TAS. So I think gaur is really the only one that'd drop. > It looks to me like this is mostly about compiler support not the > hardware; that doesn't make it not a problem, though. (I also > remain skeptical about the quality of the compiler intrinsics > on non-mainstream hardware.) I think that's fair enough for really old platforms, but at least for gcc / clang I don't think it's a huge concern for newer ones. Even if not mainstream. For gcc/clang the intrinsics basically back the C11/C++11 "language level" atomics support. And those are extremely widely used these days. Greetings, Andres Freund
Commits
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Convert SpinLock* macros to static inline functions.
- bfc321b4723e 19 (unreleased) landed
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Clean up includes of s_lock.h.
- f219167910ad 14.0 landed
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Fix deadlock danger when atomic ops are done under spinlock.
- 5fffa8fce37b 13.0 landed
- 6cc2866c4cdf 12.4 landed
- 825d89dda5ad 11.9 landed
- c2a84bee1228 10.14 landed
- 8bc13287ed3e 9.6.19 landed
- 3e69bf3b142b 9.5.23 landed
- cf1234a10e50 14.0 landed
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Add basic spinlock tests to regression tests.
- 3f66e1c5a576 10.14 landed
- e027219f2131 11.9 landed
- 008c119928a3 12.4 landed
- 59225dcefef2 13.0 landed
- 3b37a6de027c 14.0 landed
- e8302f107af9 9.6.19 landed
- 7e91f90a8ed4 9.5.23 landed
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spinlock emulation: Fix bug when more than INT_MAX spinlocks are initialized.
- dcf3cb60cbef 9.5.23 landed
- 660622053419 9.6.19 landed
- b295f666b7f0 10.14 landed
- 34d29222a0bb 11.9 landed
- b91cfaa34f44 12.4 landed
- 276bdc93924a 13.0 landed
- 4d4ca24efe8e 14.0 landed
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Avoid potential spinlock in a signal handler as part of global barriers.
- 09bff91b316e 13.0 landed
- fd49d5380757 14.0 landed
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Make pg_stat_wal_receiver consistent with the WAL receiver's shmem info
- 2c8dd05d6cbc 13.0 cited
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Improve 64bit atomics support.
- e8fdbd58fe56 10.0 cited