v2-0004-Require-memory-barrier-support.patch

From 2ccc8fdaf2f1441d9ba2924451ffa53bf1a1f4a5 Mon Sep 17 00:00:00 2001
From: Thomas Munro <thomas.munro@gmail.com>
Date: Tue, 30 Jul 2024 07:14:59 +1200
Subject: [PATCH v2 4/4] Require memory barrier support.

Previously we had a fallback implementation that made a harmless system
call, on the theory that system calls must contain a memory barrier.
(Some of the comments removed refer to a spinlock implementation, but
that changed in 1b468a13 which left some stray comments.)

We don't require 'read' and 'write' barriers, falling back to full
memory barriers still.  Notably, MSVC relies on that, which is probably
incorrect XXX?

Discussion: https://postgr.es/m/721bf39a-ed8a-44b0-8b8e-be3bd81db748%40technowledgy.de
Discussion: https://postgr.es/m/3351991.1697728588%40sss.pgh.pa.us
---
 src/backend/port/atomics.c          | 23 -----------------------
 src/include/port/atomics.h          |  4 ++++
 src/include/port/atomics/fallback.h | 16 ----------------
 src/include/port/atomics/generic.h  | 10 ----------
 4 files changed, 4 insertions(+), 49 deletions(-)

diff --git a/src/backend/port/atomics.c b/src/backend/port/atomics.c
index 19a84a7849..f98f6b6dbd 100644
--- a/src/backend/port/atomics.c
+++ b/src/backend/port/atomics.c
@@ -17,29 +17,6 @@
 #include "port/atomics.h"
 #include "storage/spin.h"
 
-#ifdef PG_HAVE_MEMORY_BARRIER_EMULATION
-#ifdef WIN32
-#error "barriers are required (and provided) on WIN32 platforms"
-#endif
-#include <signal.h>
-#endif
-
-#ifdef PG_HAVE_MEMORY_BARRIER_EMULATION
-void
-pg_spinlock_barrier(void)
-{
-	/*
-	 * NB: we have to be reentrant here, some barriers are placed in signal
-	 * handlers.
-	 *
-	 * We use kill(0) for the fallback barrier as we assume that kernels on
-	 * systems old enough to require fallback barrier support will include an
-	 * appropriate barrier while checking the existence of the postmaster pid.
-	 */
-	(void) kill(PostmasterPid, 0);
-}
-#endif
-
 
 #ifdef PG_HAVE_ATOMIC_U64_SIMULATION
 
diff --git a/src/include/port/atomics.h b/src/include/port/atomics.h
index edb0ae40dc..c0c8688f73 100644
--- a/src/include/port/atomics.h
+++ b/src/include/port/atomics.h
@@ -101,6 +101,10 @@
 #if !defined(pg_compiler_barrier_impl)
 #error "could not find an implementation of pg_compiler_barrier"
 #endif
+#if !defined(pg_memory_barrier_impl)
+#error "could not find an implementation of pg_memory_barrier_impl"
+#endif
+
 
 /*
  * Provide a spinlock-based implementation of the 64 bit variants, if
diff --git a/src/include/port/atomics/fallback.h b/src/include/port/atomics/fallback.h
index 9f83827d83..2c0eb28768 100644
--- a/src/include/port/atomics/fallback.h
+++ b/src/include/port/atomics/fallback.h
@@ -17,22 +17,6 @@
 #	error "should be included via atomics.h"
 #endif
 
-#ifndef pg_memory_barrier_impl
-/*
- * If we have no memory barrier implementation for this architecture, we
- * fall back to acquiring and releasing a spinlock.
- *
- * It's not self-evident that every possible legal implementation of a
- * spinlock acquire-and-release would be equivalent to a full memory barrier.
- * For example, I'm not sure that Itanium's acq and rel add up to a full
- * fence.  But all of our actual implementations seem OK in this regard.
- */
-#define PG_HAVE_MEMORY_BARRIER_EMULATION
-
-extern void pg_spinlock_barrier(void);
-#define pg_memory_barrier_impl pg_spinlock_barrier
-#endif
-
 
 #if !defined(PG_HAVE_ATOMIC_U64_SUPPORT)
 
diff --git a/src/include/port/atomics/generic.h b/src/include/port/atomics/generic.h
index 6113ab62a3..b636f95142 100644
--- a/src/include/port/atomics/generic.h
+++ b/src/include/port/atomics/generic.h
@@ -135,19 +135,9 @@ pg_atomic_unlocked_test_flag_impl(volatile pg_atomic_flag *ptr)
 static inline void
 pg_atomic_clear_flag_impl(volatile pg_atomic_flag *ptr)
 {
-	/*
-	 * Use a memory barrier + plain write if we have a native memory
-	 * barrier. But don't do so if memory barriers use spinlocks - that'd lead
-	 * to circularity if flags are used to implement spinlocks.
-	 */
-#ifndef PG_HAVE_MEMORY_BARRIER_EMULATION
 	/* XXX: release semantics suffice? */
 	pg_memory_barrier_impl();
 	pg_atomic_write_u32_impl(ptr, 0);
-#else
-	uint32 value = 1;
-	pg_atomic_compare_exchange_u32_impl(ptr, &value, 0);
-#endif
 }
 
 #elif !defined(PG_HAVE_ATOMIC_TEST_SET_FLAG)
-- 
2.39.2