wip-standardize-macros-for-detecting-architectures.patch
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Filename: wip-standardize-macros-for-detecting-architectures.patch
Type: text/x-diff
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| File | + | − |
|---|---|---|
| src/include/c.h | 53 | 1 |
diff --git a/src/include/c.h b/src/include/c.h index 97ed8c63f5e..85cf2604898 100644 --- a/src/include/c.h +++ b/src/include/c.h @@ -106,6 +106,58 @@ extern "C++" * ---------------------------------------------------------------- */ +/* + * Not all compilers follow gcc's names of macros for particular target + * architectures. Let's standardize on gcc's names (with trailing __), + * and cause those to become defined here if they are not already. + * + * Note: while this list is alphabetical, it's necessary to check _M_ARM64 + * before _M_AMD64, because Microsoft's ARM64EC environment defines both. + */ +#if defined(__arm__) || defined(__arm) +#ifndef __arm__ +#define __arm__ 1 +#endif +#elif defined(__aarch64__) || defined(_M_ARM64) +#ifndef __aarch64__ +#define __aarch64__ 1 +#endif +#elif defined(__mips__) +/* no work */ +#elif defined(__mips64__) +/* no work */ +#elif defined(__powerpc__) || defined(__ppc__) +#ifndef __powerpc__ +#define __powerpc__ 1 +#endif +#elif defined(__powerpc64__) || defined(__ppc64__) +#ifndef __powerpc64__ +#define __powerpc64__ 1 +#endif +#elif defined(__riscv__) +/* no work */ +#elif defined(__riscv64__) +/* no work */ +#elif defined(__s390__) +/* no work */ +#elif defined(__s390x__) +/* no work */ +#elif defined(__sparc__) || defined(__sparc) +#ifndef __sparc__ +#define __sparc__ 1 +#endif +#elif defined(__i386__) || defined (__386) || defined(_M_IX86) +#ifndef __i386__ +#define __i386__ 1 +#endif +#elif defined(__x86_64__) || defined(__x86_64) || defined (__amd64) || defined(_M_AMD64) +#ifndef __x86_64__ +#define __x86_64__ 1 +#endif +#else +#error "cannot identify target architecture" +#endif + /* * Disable "inline" if PG_FORCE_DISABLE_INLINE is defined. * This is used to work around compiler bugs and might also be useful for @@ -1337,7 +1389,7 @@ typedef struct PGAlignedXLogBlock PGAlignedXLogBlock; * SSE2 instructions are part of the spec for the 64-bit x86 ISA. We assume * that compilers targeting this architecture understand SSE2 intrinsics. */ -#if (defined(__x86_64__) || defined(_M_AMD64)) +#if defined(__x86_64__) #define USE_SSE2 /*